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a
FEATURES Simple: Basic Function is W = XY + Z Complete: Minimal External Components Required Very Fast: Settles to 0.1% of FS in 20 ns DC-Coupled Voltage Output Simplifies Use High Differential Input Impedance X, Y and Z Inputs Low Multiplier Noise: 50 nV/Hz APPLICATIONS Very Fast Multiplication, Division, Squaring Wideband Modulation and Demodulation Phase Detection and Measurement Sinusoidal Frequency Doubling Video Gain Control and Keying Voltage Controlled Amplifiers and Filters
X1 X2
250 MHz, Voltage Output 4-Quadrant Multiplier AD835
FUNCTIONAL BLOCK DIAGRAM
X = X1 -X2
AD835
XY
XY + Z
+1
W OUTPUT
Y1 Y2 Y = Y1 -Y2
Z INPUT
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD835 is a complete four-quadrant voltage output analog multiplier fabricated on an advanced dielectrically isolated complementary bipolar process. It generates the linear product of its X and Y voltage inputs, with a -3 dB output bandwidth of 250 MHz (a small signal rise time of 1 ns). Full-scale (-1 V to +1 V) rise/fall times are 2.5 ns (with the standard RL of 150 ) and the settling time to 0.1% under the same conditions is typically 20 ns. Its differential multiplication inputs (X, Y) and its summing input (Z) are at high impedance. The low impedance output voltage (W) can provide up to 2.5 V and drive loads as low as 25 . Normal operation is from 5 V supplies. Though providing state-of-the-art speed, the AD835 is simple to use and versatile. For example, as well as permitting the addition of a signal at the output, the Z input provides the means to operate the AD835 with voltage gains up to about x10. In this capacity, the very low product noise of this multiplier (50 nVHz) makes it much more useful than earlier products. The AD835 is available in an 8-pin plastic mini-DIP package (N) and an 8-pin SOIC (R) and is specified to operate over the -40C to +85C industrial temperature range.
1. The AD835 is the first monolithic 250 MHz four quadrant voltage output multiplier. 2. Minimal external components are required to apply the AD835 to a variety of signal processing applications. 3. High input impedances (100 k 2 pF) make signal source loading negligible. 4. High output current capability allows low impedance loads to be driven. 5. State of the art noise levels achieved through careful device optimization and the use of a special low noise bandgap voltage reference. 6. Designed to be easy to use and cost effective in applications which formerly required the use of hybrid or board level solutions.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1994 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD835-SPECIFICATIONS
Model
TRANSFER FUNCTION Parameter INPUT CHARACTERISTICS (X, Y) Differential Voltage Range Differential Clipping Level Low Frequency Nonlinearity vs. Temperature Common-Mode Voltage Range Offset Voltage vs. Temperature CMRR Bias Current vs. Temperature Offset Bias Current Differential Resistance Single-Sided Capacitance Feedthrough, X Feedthrough, Y DYNAMIC CHARACTERISTICS -3 dB Small-Signal Bandwidth -0.1 dB Gain Flatness Frequency Slew Rate Differential Gain Error, X Differential Phase Error, X Differential Gain Error, Y Differential Phase Error, Y Harmonic Distortion Settling Time, X or Y SUMMING INPUT (Z) Gain -3 dB Small-Signal Bandwidth Differential Input Resistance Single Sided Capacitance Maximum Gain Bias Current OUTPUT CHARACTERISTICS Voltage Swing vs. Temperature Voltage Noise Spectral Density Offset Voltage vs. Temperature2 Short Circuit Current Scale Factor Error vs. Temperature Linearity (Relative Error)3 vs. Temperature POWER SUPPLIES Supply Voltage For Specified Performance Quiescent Supply Current vs. Temperature PSRR at Output vs. Vp PSRR at Output vs. Vn
(TA = +25 C, VS =
5 V, RL = 150
, CL 5 pF unless otherwise noted)
AD835AN/AR
W= ( X1 - X 2)(Y1 - Y 2) U +Z
Conditions VCM = 0 X = 1 V, Y = 1 V Y = 1 V, X = 1 V TMIN to TMAX1 X = 1 V, Y = 1 V Y = 1 V, X = 1 V TMIN to TMAX1 f 100 kHz; 1 V p-p TMIN to TMAX1
Min
Typ 1 1.4 0.3 0.1
Max
Unit V V % FS % FS % FS % FS V mV mV dB A A A k pF dB dB MHz MHz V/s % Degrees % Degrees dB dB ns
1.2
0.5 0.3 0.7 0.5 +3 20 25 20 27
-2.5 70
3 10 2 100 2
X = 1 V, Y = 0 V Y = 1 V, X = 0 V 150 W = -2.5 V to +2.5 V f = 3.58 MHz f = 3.58 MHz f = 3.58 MHz f = 3.58 MHz X or Y = 10 dBm, 2nd and 3rd Harmonic Fund = 10 MHz Fund = 50 MHz To 0.1%, W = 2 V p-p From Z to W, f 10 MHz 0.990
-46 -60 250 15 1000 0.3 0.2 0.1 0.1 -70 -40 20 0.995 250 60 2 50 50 2.5 50 25 75 5 0.5 75 10 8 9 1.0 1.25
X, Y to W, Z Shorted to W, f = 1 kHz
MHz k pF dB A V V nV/Hz mV mV mA % FS % FS % FS % FS
TMIN to TMAX1 X = Y = 0, f < 10 MHz TMIN to TMAX1 TMIN to TMAX1 TMIN to TMAX1
2.2 2.0
4.5 TMIN to TMAX1 +4.5 V to +5.5 V -4.5 V to -5.5 V
5 16
5.5 25 26 0.5 0.5
V mA mA %/V %/V
NOTES 1 TMIN = -40C, TMAX = +85C. 2 Normalized to zero at +25C. 3 Linearity is defined as residual error after compensating for input offset, output voltage offset and scale factor errors. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Specifications subject to change without notice.
-2-
REV. A
AD835
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 300 mW Operating Temperature Range . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . . +300C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Thermal Characteristics: 8-Pin Plastic DIP (N): JC = 35C/W; JA = 90C/W 8-Pin Plastic SOIC (R): JC = 45C/W; JA = 115C/W.
PIN CONNECTIONS 8-Pin Plastic DIP (N) 8-Pin Plastic SOIC (R)
Y1 Y2 VN Z 1 2 3 4 8 X1 X2 VP W
AD835
TOP VIEW (Not to Scale)
7 6 5
ORDERING GUIDE
Model AD835AN AD835AR
Temperature Range -40C to +85C -40C to +85C
Package Options* N-8 R-8
*N = Plastic DIP; R = Small Outline IC Plastic Package (SOIC).
Typical Performance Characteristics
DG DP (NTSC) FIELD = 1 LINE = 18 0.00 0.06 0.11 0.4 Wfm FCC COMPOSITE 0.16 0.19 0.20
X, Y, Z CH = 0dBm RL = 150 CL 5pF
DIFFERENTIAL GAIN - %
0.2 0.0 -0.2 -0.4 1ST 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 1ST 2ND 3RD 4TH MIN = 0.00 MAX = 0.06 p-p = 0.06 5TH 6TH
-8 -10
MAGNITUDE - dB
GAIN 0 -2 PHASE -4 -6 -90 -180 90 0
2ND 0.02
3RD 0.02
4TH 0.03
5TH 0.03
6TH 0.06
0.00
DIFFERENTIAL PHASE - Degrees
1M
10M 100M FREQUENCY - Hz
1G
Figure 1. Typical Composite Output Differential Gain & Phase, NTSC for X Channel; f = 3.58 MHz, RL = 150
DG DP (NTSC) FIELD = 1 LINE = 18 0.00 0.01 -0.00 0.3 Wfm 0.00 FCC COMPOSITE -0.01 -0.20 MIN = -0.02 MAX = 0.01 p-p/MAX = 0.03
Figure 3. Gain & Phase vs. Frequency of X, Y, Z Inputs
DIFFERENTIAL GAIN - %
0.2 0.1 0.0 -0.1 -0.3
X, Y CH = OdBm RL = 150 CL 5pF 0
MAGNITUDE - dB
-0.2 1ST 0.00 2ND 0.03 3RD 0.04 4TH 0.07 5TH 0.10 6TH 0.16
-0.1 -0.2 -0.3 -0.4 -0.5
DIFFERENTIAL PHASE - Degrees
0.20 0.10 0.00 -0.10 -0.20 1ST 2ND 3RD 4TH MIN = 0.00 MAX = 0.16 p-p = 0.16 5TH 6TH
-0.6 300k 1M 10M 100M FREQUENCY - Hz 1G
Figure 2. Typical Composite Output Differential Gain & Phase, NTSC for Y Channel; f = 3.58 MHz, RL = 150
Figure 4. Gain Flatness to 0.1 dB
REV. A
-3-
PHASE - Degrees
MIN = 0.00 MAX = 0.20 p-p/MAX = 0.20
2
180
AD835
X, Y CH = 5dBm RL = 150 CL < 5pF -10
0
MAGNITUDE - dB
-30 -40 X FEEDTHROUGH -50 -60 Y FEEDTHROUGH
Y FEEDTHROUGH
40 60
X FEEDTHROUGH
80
1M
10M 100M FREQUENCY - Hz
1G
1M
10M 100M FREQUENCY - Hz
1G
Figure 5. X and Y Feedthrough vs. Frequency
Figure 8. CMRR vs. Frequency for X or Y Channel, RL = 150 , CL 5 pF
0dBm ON SUPPLY X, Y = 1V -10 PSRR ON V+
PSRR - dB
0.200V
-20 -30 -40 -50 PSRR ON V-
GND
-0.200V
-60
100mV
10ns
300k 1M 10M 100M FREQUENCY - Hz 1G
Figure 6. Small Signal Pulse Response at W Output, RL = 150 , CL 5 pF, X Channel = 0.2 V, Y Channel = 1.0 V
Figure 9. PSRR vs. Frequency for V+ and V- Supply
10MHz
1V
GND
10dB/DIV
-1V
30MHz 20MHz
500mV
10ns
Figure 7. Large Signal Pulse Response at W Output, RL = 150 , CL 5 pF, X Channel = 1.0 V, Y Channel = 1.0 V
Figure 10. Harmonic Distortion at 10 MHz; 10 dBm Input to X or Y Channels, RL = 150 , CL = 5 pF
-4-
REV. A
CMRR - dB
-20
20
AD835
15 OUTPUT OFFSET DRIFT WILL TYPICALLY BE WITHIN SHADED AREA
50MHz
10
VOS OUTPUT DRIFT - mV
5
10dB/DIV 100MHz 150MHz
0
-5
-10 OUTPUT VOS DRIFT, NORMALIZED TO 0 AT 25C -15 -55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE - C
Figure 11. Harmonic Distortion at 50 MHz, 10 dBm Input to X or Y Channel, RL = 150 , CL 5 pF
Figure 14. VOS Output Drift vs. Temperature
35 30
3RD ORDER INTERCEPT - dBm
100MHz
X CH = 6dBm Y CH = 10dBm RL = 100
25 20
200MHz 10dB/DIV
300MHz
15 10 5 0 0 20 40 60 80 100 120 140 160 RF FREQUENCY INPUT X CHANNEL - MHz 180 200
Figure 12. Harmonic Distortion at 100 MHz, 10 dBm Input to X or Y Channel, RL = 150 , CL 5 pF
Figure 15. Fixed LO on Y Channel vs. RF Frequency Input to X Channel
35 30
+2.5V
3RD ORDER INTERCEPT - dBm
X CH = 6dBm Y CH = 10dBm RL = 100
25 20 15 10
GND
-2.5V
5
1V
10ns
0 0 20 40 60 80 100 120 140 160 LO FREQUENCY ON Y CH - MHz 180 200
Figure 13. Maximum Output Voltage Swing, RL = 50 , CL 5 pF
Figure 16. Fixed IF vs. LO Frequency on Y Channel
REV. A
-5-
AD835
PRODUCT DESCRIPTION
The AD835 is a four-quadrant, voltage output, analog multiplier fabricated on an advanced, dielectrically isolated, complementary bipolar process. In its basic mode, it provides the linear product of its X and Y voltage inputs. In this mode, the -3 dB output voltage bandwidth is 250 MHz (a small signal rise time of 1 ns). Full-scale (-1 V to +1 V) rise/fall times are 2.5 ns (with the standard RL of 150 ) and the settling time to 0.1% under the same conditions is typically 20 ns. As in earlier multipliers from Analog Devices, a unique summing feature is provided at the Z-input. As well as providing independent ground references for inputs and output, and enhanced versatility, this feature allows the AD835 to operate with voltage gain. Its X-, Y- and Z-input voltages are all nominally 1 V FS, with overrange of at least 20%. The inputs are fully differential and at high impedance (100 k 2 pF) and provide a 70 dB CMRR (f 1 MHz). The low impedance output is capable of driving loads as small as 25 . The peak output can be as large as 2.2 V minimum for RL = 150 , or 2.0 V minimum into RL = 50 . The AD835 has much lower noise than the AD534 or AD734, making it attractive in low level signal-processing applications, for example, as a wideband gain-control element or modulator.
Basic Theory
Simplified representations of this sort, where all signals are presumed to be expressed in volts, are used throughout this data sheet, to avoid the needless use of less-intuitive subscripted variables (such as VX1). We can view all variables as being normalized to 1 V. For example, the input X can either be stated as being in the range -1 V to +1 V, or simply -1 to +1. The latter representation will be found to facilitate the development of new functions using the AD835. The explicit inclusion of the denominator, U, is also less helpful, as in the case of the AD835, if it is not an electrical input variable.
Scaling Adjustment
The basic value of U in Equation 1 is nominally 1.05 V. Figure 18, which shows the basic multiplier connections, also shows how the effective value of U can be adjusted to have any lower voltage (usually 1 V) through the use of a resistive-divider between W (Pin 5) and Z (Pin 4). Using the general resistor values shown, we can rewrite Equation 1 as W= XY + kW + (1 - k)Z ' U (3)
(where Z' is distinguished from the signal Z at Pin 4). It follows that XY W= + Z' (4) (1 - k)U In this way, we can modify the effective value of U to
U ' = (1 - k)U
The multiplier is based on a classic form, having a translinear core, supported by three (X, Y, Z) linearized voltage-to-current converters, and the load driving output amplifier. The scaling voltage (the denominator U, in the equations below) is provided by a bandgap reference of novel design, optimized for ultralow noise. Figure 17 shows the functional block diagram. In general terms, the AD835 provides the function
(5)
without altering the scaling of the Z' input. (This is to be expected, since the only "ground reference" for the output is through the Z' input.) Thus, to set U' to 1 V, remembering that the basic value of U is 1.05 V, we need to choose R1 to have a nominal value of 20 times R2. The values shown here allow U to be adjusted through the nominal range 0.95 V to 1.05 V, that is, R2 provides a 5% gain adjustment.
+5V +5V FB 4.7F TANTALUM
W=
(X 1 - X 2)(Y 1 - Y 2) +Z U
(1)
where the variables W, U, X, Y and Z are all voltages. Connected as a simple multiplier, with X = X1 - X2, Y = Y1 - Y2 and Z = 0, and with a scale factor adjustment (see below) which sets U = 1 V, the output can be expressed as W = XY (2)
0.01F CERAMIC X 8 7 X2 Y2 2 6 VP VN 3 5 W R1 = (1-k) R 2k Z 4 W X1 X1 Y1
X1 X2
X = X1 -X2
AD835
AD835
1
XY
XY + Z
+1
W OUTPUT
Y 4.7F TANTALUM R2 = kR 200
Y1 Y2 Y = Y1 -Y2
0.01F CERAMIC FB
Z1
Z INPUT
-5V
Figure 17. Functional Block Diagram
Figure 18. Multiplier Connections
Note that in many applications, the exact gain of the multiplier may not be very important; in which case, this network may be omitted entirely, or R2 fixed at 100 .
-6-
REV. A
AD835
APPLICATIONS
The AD835 is both easy to use and versatile. The capability for adding another signal to the output at the Z input is frequently valuable. Three applications of this feature are presented here: a wideband voltage controlled amplifier, an amplitude modulator and a frequency doubler. Of course, the AD835 may also be used as a square law detector (with its X- and Y-inputs connected in parallel) in which mode it is useful at input frequencies to well over 250 MHz, since that is the bandwidth limitation only of the output amplifier.
Multiplier Connections
12dB (VG = 1V)
6dB (VG = 0.5V)
0dB (VG = 0.25V)
Figure 18 shows the basic connections for multiplication. The inputs will often be single sided, in which case the X2 and Y2 inputs will normally be grounded. Note that by assigning Pins 7 and 2 to these (inverting) inputs, respectively, an extra measure of isolation between inputs and output is provided. The X and Y inputs may, of course, be reversed to achieve some desired overall sign with inputs of a particular polarity, or they may be driven fully differentially. Power supply decoupling and careful board layout are always important in applying wideband circuits. The decoupling recommendations shown in Figure 18 should be followed closely. In remaining figures in this data sheet, these power supply decoupling components have been omitted for clarity, but should be used wherever optimal performance with high speed inputs is required. However, they may be omitted if the full high frequency capabilities of AD835 are not being exploited.
A Wideband Voltage Controlled Amplifier
10k 100k START 10 000.000Hz
1M
10M 100M STOP 100 000 000.000Hz
Figure 20. AC Response of VCA
An Amplitude Modulator
Figure 21 shows a simple modulator. The carrier is applied both to the Y-input and the Z-input, while the modulating signal is applied to the X-input. For zero modulation, there is no product term, so the carrier input is simply replicated at unity gain by the voltage follower action from the Z-input. At X = 1 V, the RF output is doubled, while for X = -1 V, it is fully suppressed. That is, an X-input of approximately 1 V (actually U, or about 1.05 V) corresponds to a modulation index of 100%. Carrier and modulation frequencies can be up to 300 MHz, somewhat beyond the nominal -3 dB bandwidth. Of course, a suppressed carrier modulator can be implemented by omitting the feedforward to the Z-input, grounding that pin instead.
+5V MODULATION INPUT 8 X1 X1 Y1 1 7 X2 Y2 2 6 VP VN 3 -5V 5 W Z 4 MODULATED CARRIER OUTPUT
Figure 19 shows the AD835 configured to provide a gain of nominally 0 to 12 dB. (In fact, the control range extends from well under -12 dB to about +14 dB.) R1 and R2 set the gain to be nominally x4. The attendant bandwidth reduction that comes with this increased gain can be partially offset by the addition of the peaking capacitor C1. Although this circuit shows the use of dual supplies, the AD835 can operate from a single 9 V supply with slight revision.
+5V VG (GAIN CONTROL) 8 X1 X1 Y1 1 VIN (SIGNAL) -5V 7 X2 Y2 2 6 VP VN 3 5 W Z 4 R1 97.6 C1 33pF VOLTAGE OUTPUT
AD835
CARRIER OUTPUT
AD835
Figure 21. Simple Amplitude Modulator Using the AD835
R2 301
Squaring and Frequency Doubling
Amplitude domain squaring of an input signal, E, is achieved simply by connecting the X- and Y-inputs in parallel to produce an output of E2/U. The input may have either polarity, but the output in this case will always be positive. The output polarity may be reversed by interchanging either the X or Y inputs. When the input is a sine wave E sin t, a signal squarer behaves as a frequency doubler, since (6) U 2U While useful, Equation 6 shows a dc term at the output which will vary strongly with the amplitude of the input, E.
Figure 19. Voltage Controlled 50 MHz Amplifier Using the AD835
The ac response of this amplifier for gains of 0 dB (VG = 0.25 V), 6 dB (VG = 0.5 V) and 12 dB (VG = 1 V) is shown in Figure 20. In this application, the resistor values have been slightly adjusted to reflect the nominal value of U = 1.05 V. The overall sign of the gain may be controlled by the sign of VG.
( E sin t )2 = E 2 (1 - cos 2 t )
REV. A
-7-
AD835
Figure 22 shows a frequency doubler which overcomes this limitation and provides a relatively constant output over a moderately wide frequency range, determined by the time-constant C1 and R1. The voltage applied to the X- and Y-inputs are exactly in quadrature at a frequency f = 1/2 C1R1 and their amplitudes are equal. At higher frequencies, the X-input becomes smaller while the Y-input increases in amplitude; the opposite happens at lower frequencies. The result is a double frequency output, centered on ground, whose amplitude of 1 V for a 1 V input varies by only 0.5% over a frequency range of 10%. Because there is no "squared" dc component at the output, sudden changes in the input amplitude do not cause a "bounce" in the dc level.
VG C1 VOLTAGE OUTPUT 8 X1 X1 Y1 1 7 X2 Y2 2 6 VP VN 3 5 W R2 97.6 Z 4
0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) SEATING PLANE
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic DIP (N Package)
C1903a-3-12/94
0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204)
8 PIN 1 1
5 0.280 (7.11) 0.240 (6.10) 4
0.430 (10.92) 0.348 (8.84) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93)
+5V
0.130 (3.30) MIN
AD835
R1
-5V
R3 301
8-Pin Plastic SOIC (R Package)
8
5 0.1574 (4.00) 0.1497 (3.80)
Figure 22. Broadband "Zero-Bounce" Frequency Doubler
This circuit is based on the identity
cos sin = 1 sin 2 2
PIN 1 1 4
0.2440 (6.20) 0.2284 (5.80)
( 7)
0.0098 (0.25) 0.0040 (0.10)
0.1968 (5.00) 0.1890 (4.80) 0.102 (2.59) 0.094 (2.39) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8 0
0.0196 (0.50) x 45 0.0099 (0.25)
At O = 1/C1R1, the X input leads the input signal by 45 (and is attenuated by 2, while the Y input lags the input signal by 45, and is also attenuated by 2. Since the X and Y inputs are 90 out of phase, the response of the circuit will be
0.0098 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
W=
1E E E2 (sin t - 45 ) (sin t + 45 ) = (sin 2t ) (8) 2U U2 2
-8-
REV. A
PRINTED IN U.S.A.
which has no dc component, R2 and R3 are included to restore the output to 1 V for an input amplitude of 1 V (the same gain adjustment as mentioned earlier). Because the voltage across the capacitor, C1, decreases with frequency, while that across the resistor, R1, increases, the amplitude of the output varies only slightly with frequency. In fact, it is only 0.5% below its full value (at its center frequency = 1/C1R1) at 90% and 110% of this frequency.

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